Edge IP Solution

Deterministic Ethernet IP solution with
TSN (Time Sensitive Networking)

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TTTech Industrial’s Edge IP Solution offers a simple way to add TSN (Time Sensitive Networking) Ethernet functionality to switched endpoint devices, such as industrial controllers. Edge IP Solution includes IP core and associated software for fast and easy integration onto your FPGA enabling open, standard deterministic switching functionality. An Edge IP Solution reference design is available for TTTech Industrial’s Evaluation Board.

TTTech Industrial draws on more than 15 years of experience in time-scheduled networking. This enables Edge IP Solution users to benefit from guarantee of service, which allows for the convergence of controls, streaming and data traffic over one standard Ethernet network without affecting real-time performance or wasting bandwidth. In addition, customers can use TSN to configure control networks, seamlessly integrate systems and secure critical network traffic against denial-of-service and network flooding.

TTTech Industrial Edge IP Solution
White paper TSN in industrial automation

TSN Switch Features

IEEE 802.1Qbv
Scheduled Traffic

Provides guaranteed communication latency for time-critical traffic over standard Ethernet even in a converged infrastructure.

IEEE 802.1AS
Time Synchronization

Profile of IEEE 1588v2 for synchronization of clocks in the network. Supports timing requirements for scheduled TSN networks.

IEEE 802.1Qcc
SRP Enhancements

Defines the interfaces for central configuration of TSN networks. Supports configuration models for dynamic scheduling of TSN.

IEEE 802.1Qbu
Frame Preemption

Allows for optimal bandwidth utilization of non-scheduled background traffic sent in parallel with scheduled traffic.

IEEE 802.1CB Seamless Redundancy

Enables seamless redundancy for increased network availability. Allows for redundancy on a per stream basis for individual critical streams.

Technical Specifications

  • Ports
    • 3 to 5 ports; 10/100/1000 Mbit/s
  • Target device
    • Cyclone V SoC, Arria 10
  • Physical interfaces
    • MII, GMII, DMA for host
    • PPS (Pulse-Per-Second) output
    • Avalon slave interface for management register access
  • Reference design adapters
    • 100BASE-FX, 1000BASE-X
  • TSN
    • IEEE 802.1AS Time Synchronization
    • IEEE 802.1Qbv Scheduled Traffic
    • IEEE 802.1Qbu Frame Preemption
    • IEEE 802.1Qcc SRP Enhancements
  • IEEE 802.1Q
    • Port-based VLAN classification
    • Assignment to traffic class on ingress ports
    • Support for credit-based shaper (CBS)
  • Clock synchronization
    • IEEE 802.1AS (including multi-time domain support)
    • IEEE 1588-2008 layer 2 one/two-step end-to-end transparent clock support
  • Configuration
    • NETCONF 1.0/1.1 (RFC 6241) including derived YANG models
    • - IEEE 802.1Qbv Scheduled Traffic
    • - IEEE 802.1Qbu Frame Preemption
    • - IEEE 802.1Qcp Bridges and Bridged Networks (VLAN support)
    • SNMP v1/v2/v3 (RFC 3416) including MIB
  • Switching engine
    • Store and forward architecture providing full cross-sectional bandwidth
    • 128 Kbit frame buffer per port
    • 4096 VLANs
    • 16 MAC address filters per port
    • Up to 4096 entry MAC address hash based learning table
    • Up to 4096 policers per port
    • 8 traffic shapers per port (optional)
    • Static configuration of MAC addresses
    • Flow identification based MAC addresses
    • Ingress rate-limiting on a per-port basis for unicast, multicast, and broadcast traffic
  • Operating system
    • Linux Kernel 4.9 LTS, LTSI (optional real-time patch)
    • Support for Linux net_dev, switch_dev, and PHC (PTP hardware clock)
  • Embedded software
    • Linux kernel module
    • Native Linux interfaces / user space configuration library
    • Edge PTP in binary format for ARM – for IEEE 1588 / IEEE 802.1AS clock synchronization
    • MSTP including additions for engineered traffic (802.1Qcc)
    • Open source support for SNMP and NETCONF