Flex IP Core

Flexible Deterministic Ethernet IP core with
TSN (Time Sensitive Networking)

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TTTech Industrial’s Flex IP Core is a flexible design IP for customized chip or ASIC products. Flex IP Core offers a wide range of configurable features and a verification environment that enables developers to check the coverage and quality of IP. Flex IP Core source code is developed and delivered according to ASIC requirements e.g. memories instantiated on top-level.

TTTech Industrial draws on more than 15 years of experience in time-scheduled networking. This enables Flex IP Core users to benefit from guarantee of service, which allows for the convergence of controls, streaming and data traffic over one standard Ethernet network without affecting real-time performance or wasting bandwidth. In addition, customers can use TSN to configure control networks, seamlessly integrate systems and secure critical network traffic against denial-of-service and network flooding.

TSN Switch Features

IEEE 802.1Qbv
Scheduled Traffic

Provides guaranteed communication latency for time-critical traffic over standard Ethernet even in a converged infrastructure.

IEEE 802.1AS
Time Synchronization

Profile of IEEE 1588v2 for synchronization of clocks in the network. Supports timing requirements for scheduled TSN networks.

IEEE 802.1Qcc
SRP Enhancements

Defines the interfaces for central configuration of TSN networks. Supports configuration models for dynamic scheduling of TSN.

IEEE 802.1Qbu
Frame Preemption

Allows for optimal bandwidth utilization of non-scheduled background traffic sent in parallel with scheduled traffic.

IEEE 802.1CB Seamless Redundancy

Enables seamless redundancy for increased network availability. Allows for redundancy on a per stream basis for individual critical streams.

IEEE 802.1Qci
Filtering and Policing

Protects against faulty and/or malicious endpoints and switches. Isolates faults to specific regions in the network. (Available 2020)

Technical Specifications

  • Ports
    • 3 to 12 ports; 10/100/1000 Mbit/s
  • Physical interfaces
    • 100BASE-FX, 1000BASE-X
    • PPS (Pulse-Per-Second) output
    • Avalon slave interface for management register access
  • TSN
    • IEEE 802.1AS Time Synchronization
    • IEEE 802.1Qbv Scheduled Traffic
    • IEEE 802.1Qcc SRP Enhancements
    • IEEE 802.1Qbu Frame Preemption
    • IEEE 802.1CB Frame Replication and Elimination
    • IEEE 802.1Qci Filtering and Policing (Available 2020)
  • AVB
    • IEEE 802.1AS Time Synchronization for Time-Sensitive Applications (gPTP)
    • IEEE 802.1Qav Forwarding and Queuing for Time-Sensitive Streams (FQTSS)
  • HSR
    • HSR RedBox, HSR End Node and QuadBox support
  • PRP
    • PRP RedBox and DANP support
  • IEEE 802.1Q
    • Port-based VLANs and VLAN tagging
    • Prioritization of packets on egress ports
    • Untagging of VLAN frames on egress ports
  • Clock synchronization
    • IEEE 802.1AS (including multi-time domain support)
    • IEEE 1588-2008 layer 2 one/two-step end-to-end transparent clock support
  • Switching engine
    • Store and forward architecture providing full cross-sectional bandwidth
    • 128 Kbit frame buffer per port
    • 4096 VLANs
    • 16 MAC address filters per port
    • Up to 4096 entry MAC address hash-based learning table
    • Up to 4096 policer per port
    • 8 traffic shapers per port (optional)
    • Static configuration of MAC addresses
    • Flow identification based MAC addresses
    • Ingress rate-limiting on a per-port basis for unicast, multicast, and broadcast traffic
  • Embedded software
    • Linux kernel module
    • Native Linux interfaces / user space configuration library
    • Edge PTP in binary format for ARM – for IEEE 1588 / IEEE 802.1AS clock synchronization
    • MSTP including additions for engineered traffic (802.1Qcc)
    • Open source support for SNMP and NETCONF