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Introducing Edge IP Solution

Edge IP Solution offers highly configurable TSN functionality for industrial devices. Edge IP Solution includes IP core and associated software stacks for fast and easy integration onto your FPGA – enabling open, standard deterministic switching functionality. Edge IP Solution is available for Intel Cyclone V (SoC), Cyclone 10 GX and Arria 10 (SoC) FPGAs.

Edge IP Solution Building Blocks

The Edge IP Solution delivery includes configurable building blocks (highlighted in blue)

to enable TSN features in your FPGA-based device.

 

Supported TSN Standards

IEEE 802.1Qbv

Time Aware Shaping

 

Provides guaranteed communication latency for time-critical traffic over standard Ethernet even in a converged infrastructure.

 

IEEE 802.1AS

Time Synchronization



Profile of IEEE 1588v2 for synchronization of clocks in the network. Supports timing requirements for scheduled TSN networks.

IEEE 802.1Qcc

SRP Enhancements

 

Defines the interfaces for central configuration of TSN networks. Supports configuration models for dynamic scheduling of TSN.

 

IEEE 802.1Qbu

Frame Preemption



Allows for optimal bandwidth utilization of non-scheduled background traffic sent in parallel with scheduled traffic.

IEEE 802.1CB

Seamless Redundancy



Enables seamless redundancy for increased network availability. Allows for redundancy on a per stream basis for individual critical streams.

802.1Qci

Seamless Redundancy

 

Protects against faulty and/or malicious endpoints and switches. Isolates faults to specific regions in the network.

 

Configuration Options

Edge IP Solution is available for Intel Cyclone V (SoC), Cyclone 10 GX and Arria 10 (SoC) FPGAs. All individual TSN standards can be enabled or disabled on a per port basis.

  • Number of ports (2+1 – 4+1)
  • Number of queues (4/8)
  • Port extension to 7+1 available
  • Number of static FDB entries
  • Number of FIDS (0/4/64)
  • Clock Frequency (100/125)
  • Number of DMA rings
  • Counters (enable/disable)
  • Schedule Table Rows (64-2048)
  • Gigabit Ethernet (enable/disable)
  • Credit-based shapers (enable/disable)

  • MII, GMII, RMII, RGMII
  • SGMII / 1000BASE-X / 100BASE-FX

  • Avalon Master (DMA)
  • GMII (EMAC)

  • Time Interface
  • Ethernet speed interface
  • PPS

Configuration Examples

Family/Device Configuration* ALMs Memory (Mbits)

Cyclone V

5CSXFC6C6U23I7

2+1 port switched-endpoint

3 DMA Rings

128 Lookup Entries

64 TE-MSTIs, 4096 VLANs

802.1AS-2020 Time Synchronization

802.1Qbu/802.3br Frame Preemption
15,774 0.81

Cyclone V

5CSXFC6C6U23I7

2+1 port switched-endpoint

3 DMA Rings

128 Lookup Entries

64 TE-MSTIs, 4096 VLANs

802.1AS-2020 Time Synchronization

802.1Qbv Time Aware Shaping
16,514 0.82

*all setups include IEEE 802.1Qcc NETCONF/YANG configuration; further options and combinations available; TSN standards can be chosen per port (up to 4+1, extension available); IEEE 802.1Qci, IEEE 802.1CB can be selectable in addition 

 

Application Examples

 

Embedded Device

Edge IP Solution can be used for direct attachment of a management CPU to the switch core. The CPU can be used for user applications and management functions.

Slate Products Illustration

 

 

PCIe-based Device

A management CPU can be attached to Edge IP Solution via PCIe core and DMA. This can be used for PCIe cards that extend TSN functionality to existing products and allows for reuse of existing software.

Slate Products Illustration

Acceleration Module Mediabox

TSN Extensions

Acceleration Module

 

IP hardware extension for switched endpoints

 

  • Adds ultra-low latency communication for TSN networks
  • Combines 3 different field-proven technologies: Cut-Through, Summation Frame and

    Scatter-Gather Engine
  • Cut-Through timing ~ 400 ns including data manipulation and under 1 µs per hop including appropriate PHYs
  • Achieves cycle times below 10 µs

Technical Specifications

Ports 2+1/4+1 ports; 10/100/1000 Mbit/s
Target device

Intel Cyclone V (SoC), Intel Arria 10 (SoC)

Physical interfaces

MII, GMII, DMA for host

PPS (Pulse-Per-Second) output

Avalon slave interface for management register access

Supported Ethernet interfaces

MII, GMII, RMII, RGMII, SGMII

100BASE-FX, 1000BASE-X

TSN

IEEE 802.1AS-2020 Time Synchronization

IEEE 802.1Qbv Time Aware Shaping

IEEE 802.1Qbu Frame Preemption

IEEE 802.1CB Frame Replication and Elimination for Reliability

IEEE 802.1Q

Port-based VLAN classification

Assignment to traffic class on ingress ports

Support for credit-based shaper (CBS)

Clock synchronization

IEEE 802.1AS-2020 (multi-time domain support)

IEEE 1588-2019 one step end-to-end transparent clock support

Configuration

NETCONF 1.0/1.1 (RFC 6241) including derived YANG models

- IEEE 802.1Qbv Time Aware Shaping

- IEEE 802.1Qbu Frame Preemption

- IEEE 802.1Qcp Bridges and Bridged Networks (VLAN support)

SNMP v1/v2/v3 (RFC 3416) including MIB

Switching engine

Store and forward architecture providing full cross-sectional bandwidth

128-512 kbit frame buffer per port

4096 VLANs, up to 64 MSTIs

16 MAC address filters per port

Up to 4096 entry MAC address hash based learning table

Up to 4096 policers per port

8 traffic shapers per port (optional)

Static configuration of MAC addresses

Flow identification based MAC addresses

Ingress rate-limiting on a per-port basis for unicast, multicast, and broadcast traffic

Operating system

Linux kernel 5.4 LTS

Support for Linux net_dev, switch_dev, and PHC (PTP hardware clock)

Embedded software

Linux kernel module

Native Linux interfaces / user space configuration library

Edge PTP in binary format for ARM – for IEEE 1588 / IEEE 802.1AS clock synchronization

MSTP including additions for engineered traffic (802.1Qcc)

Open source support for SNMP and NETCONF

Delivery

Encrypted Qsys IP component including interface adapters to xMII

Software and device drivers for Linux

YOCTO based build system

Ready-made boot image

Reference design for the DE-Evaluation Board Edge and the Intel Arria 10 (SoC) Development Kit

MIBs and YANG models

Getting started guide

Technical documentation

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